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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Instruction Details<br />

A8.6.309 VLD1 (single element to all lanes)<br />

This instruction loads one element from memory into every element of one or two vectors. For details of the<br />

addressing mode see Advanced SIMD addressing mode on page A7-30.<br />

Encoding T1 / A1 Advanced SIMD<br />

VLD1. , [{@}]{!}<br />

VLD1. , [{@}], <br />

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

1 1 1 1 1 0 0 1 1 D 1 0 Rn Vd 1 1 0 0 size T a Rm<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd 1 1 0 0 size T a Rm<br />

if size == ‘11’ || (size == ‘00’ && a == ‘1’) then UNDEFINED;<br />

ebytes = 1 32 then UNPREDICTABLE;<br />

A8-606 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B

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