ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
CRn opc1 CRm opc2
c0 0 c0
0
MIDR, Main ID Register
1
CTR, Cache Type Register
2
TCMTR, TCM Type Register, IMPLEMENTATION DEFINED
3
TLBTR, TLB Type Register
5
MPIDR, Multiprocessor Affinity Register
{4,6,7} Aliases of Main ID Register
{c1-c7} {0-7}
CPUID registers
1 c0 0
CCSIDR, Cache Size ID Registers
1
CLIDR, Cache Level ID Register
7
AIDR, Auxiliary ID Register, IMPLEMENTATION DEFINED
2 c0 0
CSSELR, Cache Size Selection Register
c1 0 c0 {0-2}
System Control registers
c1 {0-2}
Security Extensions registers, if implemented
c2 0 c0 {0-2} Translation Table Base Registers
c3 0 c0 0
DACR, Domain Access Control Register
c5 0 {c0,c1} {0,1} Fault Status Registers
c6 0 c0 {0,2}
Fault Address Registers
c7 0 c0 4
NOP
c1 {0,6}
Cache maintenance operations, Multiprocessing Extensions
c4 0
PAR, Physical Address Register
c5 {0,1,6,7} Cache and branch predictor maintenance operations
4
CP15ISB, Instruction barrier operation
c6
{1,2} Cache maintenance operations
c8
{0-7}
VA to PA translation operations
c10 {1,2}
Cache management operations
{4,5}
Data barrier operations
c11
1
DCCMVAU, Cache barrier operation
c13 1 NOP
c14 {1,2} Cache maintenance operations
c8 0 {c3,c5,c6,c7} {0-3} TLB maintenance operations *
c9 {0-7} {c0-c2,c5-c8} {0-7} ‡ Reserved for Branch Predictor, Cache and TCM operations
{c12-c15} {0-7} ‡ Reserved for Performance monitors
c10 0 {c0,c1,c4,c8} {0-7} ‡ Reserved for TLB Lockdown operations
c2 {0,1}
TEX Remap Registers (PRRR, NMRR)
c11 {0-7} {c0-c8,c15} {0-7} ‡ Reserved for DMA operations for TCM access
c12 0 c0 {0,1}
Security Extensions registers, if implemented
c1 0
ISR, Security Extensions register, if implemented
c13 0 c0 0 † FCSEIDR, FCSE PID Register
{1-4}
Software Thread and Context ID registers
c15 {0-7} {c0-c15} {0-7} ‡ IMPLEMENTATION DEFINED Registers
Read-only Read/Write
Write-only Bold text = Accessible in User mode
‡ Access depends on the operation † Read-only if FCSE
not implemented
* Some encodings are only in the
Multiprocessing Extensions
Figure B3-10 CP15 registers in a VMSA implementation
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B3-65