ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARMv6 Differences
when the Security Extensions are implemented, a Common register, with some bits that can be
accessed only in Secure state.
The format of the CBOR is:
31 6
5 4
UNP/SBZ
The CBOR resets to 0x00000000.
Register bits [5:3] are accessible only in Secure state. In Non-secure state they are RAZ/WI.
Bits [31:6] Reserved. UNK/SBZP.
S_WT
S_IL
S_DL
NS_WT
NS_IL
NS_DL
3 2 1
S_WT, bit [5] Secure Write-Through. Controls whether Write-Through is forced for regions marked as
Secure and Write-Back. The possible values of this bit are:
0 Do not force Write-Through. This corresponds to normal cache operation.
1 Force Write-Through for regions marked as Secure and Write-Back.
S_IL, bit [4] Secure instruction cache linefill. Can be used to disable instruction cache linefill for Secure
regions. The possible values of this bit are:
0 Instruction cache linefill enabled. This corresponds to normal cache operation.
1 Instruction cache linefill disabled for regions marked as Secure.
S_DL, bit [3] Secure data cache linefill. Can be used to disable data cache linefill for Secure regions. The
possible values of this bit are:
0 Data cache linefill enabled. This corresponds to normal cache operation.
1 Data cache linefill disabled for regions marked as Secure.
NS_WT, bit [2]
Non-secure Write-Through. Controls whether Write-Through is forced for regions marked
as Non-secure and Write-Back. The possible values of this bit are:
0 Do not force Write-Through. This corresponds to normal cache operation.
1 Force Write-Through for regions marked as Non-secure and Write-Back.
NS_IL, bit [1] Non-secure instruction cache linefill. Can be used to disable instruction cache linefill for
Non-secure regions. The possible values of this bit are:
0 Instruction cache linefill enabled. This corresponds to normal cache operation.
1 Instruction cache linefill disabled for regions marked as Non-secure.
AppxG-50 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B
0