ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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A.2 Recommended debug slave port<br />

This slave port is not required in v6 Debug <strong>and</strong> v6.1 Debug.<br />

Recommended External Debug Interface<br />

The memory-mapped interface is optional on v7 Debug. This section describes the recommended APBv3<br />

slave port. It provides both the memory-mapped <strong>and</strong> external debug interfaces.<br />

A valid external debug interface for v7 Debug is any access mechanism that enables the external debugger<br />

to complete reads or writes to the memory-mapped registers described in The memory-mapped <strong>and</strong><br />

recommended external debug interfaces on page C6-43.<br />

In v7 Debug a memory-mapped interface can be implemented to provide access to the debug registers using<br />

load <strong>and</strong> store operations. Such an interface is sufficient for the requirements of the external debug interface,<br />

<strong>and</strong> therefore it is possible to implement both the memory-mapped <strong>and</strong> external debug interfaces using a<br />

single memory slave port on the processor.<br />

This section describes the v7 Debug recommendations for an APBv3 memory slave port APBv3 as part of<br />

the external debug interface. In addition, <strong>ARM</strong> recommends a Debug Access Port capable of mastering an<br />

APBv3 bus <strong>and</strong> compatible with the <strong>ARM</strong> Debug Interface v5 (ADIv5). Figure A-3 shows the<br />

recommendations.<br />

Authentication<br />

interface<br />

DCC<br />

h<strong>and</strong>shake<br />

Cross-trigger<br />

interface<br />

Power<br />

controller<br />

interface<br />

DBGEN<br />

SPIDEN<br />

NIDEN<br />

SPNIDEN<br />

COMMTX<br />

COMMRX<br />

DBGTRIGGER<br />

DBGCPUDONE<br />

DBGACK<br />

EDBGRQ<br />

DBGRESTARTED<br />

DBGRESTART<br />

DBGNOPWRDWN<br />

DBGPWRDUP<br />

Processor<br />

PSELDBG<br />

PADDRDBG<br />

PRDATADBG<br />

PWDATADBG<br />

PENABLEDBG<br />

PREADYDBG<br />

PSLVERRDBG<br />

PWRITEDBG<br />

PCLKDBG<br />

PCLKENDBG<br />

PRESETDBGn<br />

DBGROMADDR<br />

DBGROMADDRV<br />

DBGSELFADDR<br />

DBGSELFADDRV<br />

DBGOSLOCKINIT<br />

DBGSWENABLE<br />

Debug bus<br />

interface, APBv3<br />

Configuration<br />

Figure A-3 Recommended external debug interface, including APBv3 slave port<br />

In Figure A-3, signals with a lower-case n suffix are active LOW <strong>and</strong> all other signals are active HIGH.<br />

<strong>ARM</strong> recommends that the debug registers are accessible through an <strong>ARM</strong> AMBA 3 Peripheral Bus version<br />

1 (APBv3) external debug interface. This APBv3 interface:<br />

is 32 bits wide<br />

supports only 32-bit reads <strong>and</strong> writes<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. AppxA-13

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