ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
LDMIB {!},
where:
See Standard assembler syntax fields on page A8-7.
The base register. The SP can be used.
! Causes the instruction to write a modified value back to . Encoded as W = 1.
Instruction Details
If ! is omitted, the instruction does not change in this way. Encoded as W = 0.
Is a list of one or more registers to be loaded, separated by commas and surrounded by
{ and }. The lowest-numbered register is loaded from the lowest memory address, through
to the highest-numbered register from the highest memory address.
The SP can be in the list. However, instructions that include the SP in the list are deprecated.
The PC can be in the list. If it is, the instruction branches to the address (data) loaded to the
PC. In ARMv5T and above, this branch is an interworking branch, see Pseudocode details
of operations on ARM core registers on page A2-12.
Instructions that include both the LR and the PC in the list are deprecated.
Instructions with the base register in the list and ! specified are only available before
ARMv7, and the use of such instructions is deprecated. The value of the base register after
such an instruction is UNKNOWN.
LDMED is a pseudo-instruction for LDMIB, referring to its use for popping data from Empty Descending stacks.
The pre-UAL syntaxes LDMIB and LDMED are equivalent to LDMIB.
Operation
if ConditionPassed() then
EncodingSpecificOperations();
address = R[n] + 4;
for i = 0 to 14
if registers == ‘1’ then
R[i] = MemA[address,4]; address = address + 4;
if registers == ‘1’ then
LoadWritePC(MemA[address,4]);
if wback && registers == ‘0’ then R[n] = R[n] + 4*BitCount(registers);
if wback && registers == ‘1’ then R[n] = bits(32) UNKNOWN;
Exceptions
Data Abort.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-117