ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Protected Memory System Architecture (PMSA)
If no TCMs are implemented, the TCMTR must be implemented with this ARMv6 format:
31 29 28 19 18 16 15 3 2 0
0 0 0 UNKNOWN 0 0 0 UNKNOWN 0 0 0
For details of the ARMv6 optional implementation of the TCM Type Register see c0, TCM Type Register
(TCMTR) on page AppxG-33.
Accessing the TCMTR
To access the TCMTR you read the CP15 registers with set to 0, set to c0, set to c0, and
set to 2. For example:
MRC p15,0,,c0,c0,2 ; Read CP15 TCM Type Register
B4.6.9 c0, MPU Type Register (MPUIR)
The MPU Type Register, MPUIR, identifies the features of the MPU implementation. In particular it
identifies:
whether the MPU implements:
— a Unified address map, also referred to as a von Neumann architecture
— separate Instruction and Data address maps, also referred to as a Harvard architecture.
the number of memory regions implemented by the MPU.
The MPUIR is:
a 32-bit read-only register
accessible only in privileged modes
implemented only when the PMSA is implemented.
The format of the MPUIR is:
31 24 23 16 15 8 7 1 0
UNKNOWN IRegion DRegion UNKNOWN nU
Bits [31:24] UNKNOWN.
IRegion, bits [23:16]
DRegion, bits [15:8]
Bits [7:1] UNKNOWN.
Specifies the number of Instruction regions implemented by the MPU.
If the MPU implements a Unified memory map this field is UNK/SBZ.
Specifies the number of Data or Unified regions implemented by the MPU.
If this field is zero, no MPU is implemented, and the default memory map is in use.
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