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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Instruction Details<br />

A8.6.64 LDRB (register)<br />

Load Register Byte (register) calculates an address from abase register value <strong>and</strong> an offset register value,<br />

loads a byte from memory, zero-extends it to form a 32-bit word, <strong>and</strong> writes it to a register. The offset<br />

register value can optionally be shifted. For information about memory accesses see Memory accesses on<br />

page A8-13.<br />

Encoding T1 <strong>ARM</strong>v4T, <strong>ARM</strong>v5T*, <strong>ARM</strong>v6*, <strong>ARM</strong>v7<br />

LDRB ,[,]<br />

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

0 1 0 1 1 1 0 Rm Rn Rt<br />

t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);<br />

index = TRUE; add = TRUE; wback = FALSE;<br />

(shift_t, shift_n) = (SRType_LSL, 0);<br />

Encoding T2 <strong>ARM</strong>v6T2, <strong>ARM</strong>v7<br />

LDRB.W ,[,{,LSL #}]<br />

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

1 1 1 1 1 0 0 0 0 0 0 1 Rn Rt 0 0 0 0 0 0 imm2 Rm<br />

if Rt == ‘1111’ then SEE PLD;<br />

if Rn == ‘1111’ then SEE LDRB (literal);<br />

t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);<br />

index = TRUE; add = TRUE; wback = FALSE;<br />

(shift_t, shift_n) = (SRType_LSL, UInt(imm2));<br />

if t == 13 || BadReg(m) then UNPREDICTABLE;<br />

Encoding A1 <strong>ARM</strong>v4*, <strong>ARM</strong>v5T*, <strong>ARM</strong>v6*, <strong>ARM</strong>v7<br />

LDRB ,[,+/-{, }]{!}<br />

LDRB ,[],+/-{, }<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

cond 0 1 1 P U 1 W 1 Rn Rt imm5 type 0 Rm<br />

if P == ‘0’ && W == ‘1’ then SEE LDRBT;<br />

t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);<br />

index = (P == ‘1’); add = (U == ‘1’); wback = (P == ‘0’) || (W == ‘1’);<br />

(shift_t, shift_n) = DecodeImmShift(type, imm5);<br />

if t == 15 || m == 15 then UNPREDICTABLE;<br />

if wback && (n == 15 || n == t) then UNPREDICTABLE;<br />

if ArchVersion() < 6 && wback && m == n then UNPREDICTABLE;<br />

A8-132 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B

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