ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
DBGnoPWRDWN, bit [0]
No power-down bit, DBGnoPWRDWN. This bit controls the DBGNOPWRDWN signal,
if it is implemented. The possible values of this bit are:
0 drive DBGNOPWRDWN LOW
1 drive DBGNOPWRDWN HIGH.
DBGNOPWRDWN is an IMPLEMENTATION DEFINED feature. If it is implemented, setting
this bit drives the DBGNOPWRDWN signal HIGH, requesting the power controller to
work in an emulation mode where the processor is not actually powered down when
requested. For more information, see DBGNOPWRDWN on page AppxA-9.
If the DBGNOPWRDWN signal is not implemented this bit is RAZ/WI.
C10.3.5 Device Power-down and Reset Status Register (DBGPRSR), v7 Debug only
The Device Power-down and Reset Status Register, DBGPRSR, holds information about the reset and
power-down state of the processor.
The DBGPRSR is:
debug register 197, at offset 0x314
a read-only register, with reads of the register also resetting some register bits
implemented only in v7 Debug
when the Security Extensions are implemented, a Common register.
In v6 Debug and v6.1 Debug, register 197 is not defined.
The format of the DBGPRSR is:
31 4
Reserved, UNK
Bits [31:4] Reserved, UNK.
Sticky Reset status, bit [3]
Sticky Reset status
Reset status
Sticky Power-down status
Power-up status
The meanings of the Sticky Reset status bit values are:
0 the non-debug logic of the processor has not been reset since the last time this
register was read
1 the non-debug logic of the processor has been reset since the last time this
register was read.
This bit is cleared to 0 on a read of the DBGPRSR when the non-debug logic of the
processor is not in reset state.
C10-34 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B
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