ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The System Level Programmers’ Model
Table B1-8 A and F bit values on exception entry, with Security Extensions and NS == 1 (continued)
Exception
All internal aborts
IRQ
FIQ
CPSR.E bit value on exception entry
On exception entry, the CPSR.E bit is set to the value of the SCTLR.EE bit. This bit of the CPSR controls
the load and store endianness for data handling by the exception handler, see the bit description in Format
of the CPSR and SPSRs on page B1-16. For the description of the SCTLR see:
c1, System Control Register (SCTLR) on page B3-96 for a VMSA implementation
c1, System Control Register (SCTLR) on page B4-45 for a PMSA implementation.
B1.6.4 Exception return
In the ARM architecture, exception return requires the simultaneous restoration of the PC and CPSR to
values that are consistent with the desired state of execution on returning from the exception. Normally, this
is the state of execution just before the exception was taken, but it can be different in some circumstances,
for example if the exception handler performed instruction emulation.
Typically, this involves returning to one of:
SCR bits
Exception
NS == 1, Non-secure
EA IRQ FIQ AW FW
mode
CPSR.A CPSR.F
x x x 0 x Abort Unchanged Unchanged
x x x 1 x Abort 1 Unchanged
x 0 x 0 x IRQ Unchanged Unchanged
x 0 x 1 x IRQ 1 Unchanged
x 1 x x x Monitor 1 1
x x 0 0 0 FIQ Unchanged Unchanged
x x 0 0 1 FIQ Unchanged 1
x x 0 1 0 FIQ 1 Unchanged
x x 0 1 1 FIQ 1 1
x x 1 x x Monitor 1 1
the instruction boundary at which an asynchronous exception was taken
the instruction following an SVC or SMC instruction, for an exception generated by one of those
instructions
the instruction that caused the exception, after the reason for the exception has been removed
B1-38 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B