ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The Instruction Sets
These instructions can optionally set the condition code flags, according to the result of the operation. If
they do not set the flags, existing flag settings from a previous instruction are preserved.
Table A4-2 summarizes the main data-processing instructions in the Thumb and ARM instruction sets.
Generally, each of these instructions is described in three sections in Chapter A8 Instruction Details, one
section for each of the following:
INSTRUCTION (immediate) where the second operand is a modified immediate constant.
INSTRUCTION (register) where the second operand is a register, or a register shifted by a constant.
INSTRUCTION (register-shifted register) where the second operand is a register shifted by a value
obtained from another register. These are only available in the ARM instruction set.
Instruction Mnemonic Notes
Add with Carry ADC -
Table A4-2 Standard data-processing instructions
Add ADD Thumb instruction set permits use of a modified immediate
constant or a zero-extended 12-bit immediate constant.
Form PC-relative Address ADR First operand is the PC. Second operand is an immediate constant.
Thumb instruction set uses a zero-extended 12-bit immediate
constant. Operation is an addition or a subtraction.
Bitwise AND AND -
Bitwise Bit Clear BIC -
Compare Negative CMN Sets flags. Like ADD but with no destination register.
Compare CMP Sets flags. Like SUB but with no destination register.
Bitwise Exclusive OR EOR -
Copy operand to destination MOV Has only one operand, with the same options as the second
operand in most of these instructions. If the operand is a shifted
register, the instruction is an LSL, LSR, ASR, or ROR instruction
instead. For details see Shift instructions on page A4-10.
The ARM and Thumb instruction sets permit use of a modified
immediate constant or a zero-extended 16-bit immediate constant.
Bitwise NOT MVN Has only one operand, with the same options as the second
operand in most of these instructions.
Bitwise OR NOT ORN Not available in the ARM instruction set.
Bitwise OR ORR -
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A4-9