ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Reserved encodings in the IFSR and DFSR encodings tables
Protected Memory System Architecture (PMSA)
A single encoding is reserved for cache lockdown faults. The details of these faults and any associated
subsidiary registers are IMPLEMENTATION DEFINED.
A single encoding is reserved for aborts associated with coprocessors. The details of these faults are
IMPLEMENTATION DEFINED.
B4.5.5 Distinguishing read and write accesses on Data Abort exceptions
On a Data Abort exception, the DFSR.WnR bit, bit [11] of the register, indicates whether the abort occurred
on a read access or on a write access. However, for a fault on a CP15 cache maintenance operation this bit
always indicates a write access fault.
For a fault generated by a SWP or SWPB instruction, the WnR bit is 0 if a read to the location would have
generated a fault, otherwise it is 1.
B4.5.6 Provision for classification of external aborts
An implementation can use the DFSR.ExT and IFSR.ExT bits to provide more information about external
aborts:
DFSR.ExT can provide an IMPLEMENTATION DEFINED classification of external aborts on data
accesses
IFSR.ExT can provide an IMPLEMENTATION DEFINED classification of external aborts on instruction
accesses
For all aborts other than external aborts these bits return a value of 0.
B4.5.7 Auxiliary Fault Status Registers
ARMv7 architects two Auxiliary Fault Status Registers:
the Auxiliary Data Fault Status Register (ADFSR)
the Auxiliary Instruction Fault Status Register (AIFSR).
These registers enable additional fault status information to be returned:
The position of these registers is architecturally-defined, but the content and use of the registers is
IMPLEMENTATION DEFINED.
An implementation that does not need to report additional fault information must implement these
registers as UNK/SBZ. This ensures that a privileged attempt to access these registers is not faulted.
An example use of these registers would be to return more information for diagnosing parity errors.
See c5, Auxiliary Data and Instruction Fault Status Registers (ADFSR and AIFSR) on page B4-56 for the
architectural details of these registers.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B4-21