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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Recommended External Debug Interface<br />

A.1.7 DBGPWRDUP<br />

DBGPWRDUP is not required in v6 Debug <strong>and</strong> v6.1 Debug.<br />

DBGPWRDUP is not required in a SinglePower system, that is, it is not required in a design that has only<br />

one power domain.<br />

The DBGPWRDUP input signal is HIGH when the processor is powered up, <strong>and</strong> LOW otherwise. The<br />

DBGPWRDUP signal is reflected in bit [0] of the Device Power-Down <strong>and</strong> Reset Status Register.<br />

See also Device Power-down <strong>and</strong> Reset Status Register (DBGPRSR), v7 Debug only on page C10-34 <strong>and</strong><br />

Permissions in relation to power-down on page C6-28.<br />

A.1.8 DBGROMADDR <strong>and</strong> DBGROMADDRV<br />

DBGROMADDR <strong>and</strong> DBGROMADDRV are not required in v6 Debug <strong>and</strong> v6.1 Debug. They are<br />

required in v7 Debug if the memory-mapped interface is implemented.<br />

DBGROMADDR specifies bits [31:12] of the ROM Table table physical address. This is a configuration<br />

input. It must be either:<br />

be a tie-off<br />

change only while the processor is in reset.<br />

In a system with multiple ROM Tables, this address must be tied off to the top-level ROM Table address.<br />

In a system with no ROM Table this address must be tied off with the physical address where the debug<br />

registers are memory-mapped. Debug software can use the debug component identification registers at the<br />

end of the 4KB block addressed by DBGROMADDR to distinguish a ROM table from a processor.<br />

Note<br />

If the system implements more than one debug component, for example a processor <strong>and</strong> a trace macrocell,<br />

a ROM Table must be provided.<br />

DBGROMADDRV is the valid signal for DBGROMADDR. If the address cannot be determined,<br />

DBGROMADDR must be tied off to zero <strong>and</strong> DBGROMADDRV tied LOW.<br />

The format of ROM Tables is defined in the <strong>ARM</strong> Debug Interface v5 <strong>Architecture</strong> Specification.<br />

A.1.9 DBGSELFADDR <strong>and</strong> DBGSELFADDRV<br />

DBGSELFADDR <strong>and</strong> DBGSELFADDRV are not required in v6 Debug <strong>and</strong> v6.1 Debug.<br />

In v7 Debug, DBGSELFADDR <strong>and</strong> DBGSELFDDRV are required if the memory-mapped interface is<br />

implemented. If DBGROMADDR <strong>and</strong> DBGROMADDRV are not implemented, DBGSELFADDR <strong>and</strong><br />

DBGSELFADDRV must not be implemented.<br />

AppxA-10 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B

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