ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Endian_instrs, bits [3:0]
The CPUID Identification Scheme
Indicates the supported Endian instructions. Permitted values are:
0b0000 None supported.
0b0001 Adds support for the SETEND instruction, and the E bit in the PSRs.
c0, Instruction Set Attribute Register 2 (ID_ISAR2)
The format of the ID_ISAR2 is:
31 28 27 24 23 20 19
16 15 12 11 8 7 4 3 0
Reversal
_instrs
PSR_AR
_instrs
Reversal_instrs, bits [31:28]
PSR_AR_instrs, bits [27:24]
MultU
_instrs
MultS
_instrs
Mult
_instrs
MultiAccess
Int_instrs
Indicates the supported Reversal instructions. Permitted values are:
0b0000 None supported.
0b0001 Adds support for the REV, REV16, and REVSH instructions.
0b0010 As for 0b0001, and adds support for the RBIT instruction.
Indicates the supported A and R profile instructions to manipulate the PSR. Permitted values
are:
0b0000 None supported.
0b0001 Adds support for the MRS and MSR instructions, and the exception return forms of
data-processing instructions described in SUBS PC, LR and related instructions
on page B6-25.
Note
The exception return forms of the data-processing instructions are:
In the ARM instruction set, data-processing instructions with the PC as the
destination and the S bit set. These instructions might be affected by the WithShifts
attribute.
In the Thumb instruction set, the SUBS PC,LR,#N instruction.
MemHint
_instrs
LoadStore
_instrs
MultU_instrs, bits [23:20]
Indicates the supported advanced unsigned Multiply instructions. Permitted values are:
0b0000 None supported.
0b0001 Adds support for the UMULL and UMLAL instructions.
0b0010 As for 0b0001, and adds support for the UMAAL instruction.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B5-27