ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
Instruction Details
VRSQRTS.F32 {,} , Encoded as Q = 1, sz = 0
VRSQRTS.F32 {,} , Encoded as Q = 0, sz = 0
where:
See Standard assembler syntax fields on page A8-7. An ARM VRSQRTS instruction
must be unconditional.
, , The destination vector and the operand vectors for a quadword operation.
, , The destination vector and the operand vectors for a doubleword operation.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
for r = 0 to regs-1
for e = 0 to elements-1
Elem[D[d+r],e,esize] = FPRSqrtStep(Elem[D[n+r],e,esize], Elem[D[m+r],e,esize]);
Exceptions
Undefined Instruction.
Floating-point exceptions: Input Denormal, Invalid Operation, Overflow, Underflow, and Inexact.
Newton-Raphson iteration
For details of the operation performed and how it can be used in a Newton-Raphson iteration to calculate
the reciprocal of the square root of a number, see Reciprocal square root on page A2-61.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-745