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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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An exception is described as synchronous if both of the following apply:<br />

The System Level Programmers’ Model<br />

— the exception is generated as a result of direct execution or attempted execution of the<br />

instruction stream<br />

— the return address presented to the exception h<strong>and</strong>ler is guaranteed to indicate the instruction<br />

that caused the exception.<br />

An exception is described as asynchronous if either of the following applies:<br />

— the exception is not generated as a result of direct execution or attempted execution of the<br />

instruction stream<br />

— the return address presented to the exception h<strong>and</strong>ler is not guaranteed to indicate the<br />

instruction that caused the exception.<br />

Asynchronous exceptions are of two types:<br />

a precise asynchronous exception guarantees that the state presented to the exception h<strong>and</strong>ler is<br />

consistent with the state at an identifiable instruction boundary in the execution stream from which<br />

the exception was taken.<br />

an imprecise asynchronous exception is one where the state presented to the exception h<strong>and</strong>ler is not<br />

guaranteed to be consistent with any point in the execution stream from which the exception was<br />

taken.<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. B1-5

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