ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Register Interfaces
To have full debug support for power-down and re-powering of the processor, the following registers and
individual bits need to be in the debug power domain:
DBGECR This enables the debugger to set the OS Unlock Catch bit to 1 any time and still break on
completion of the power-up sequence. If this register was in the core power domain, the
power-down event would clear this catch bit to 0. For more information, see Event Catch
Register (DBGECR) on page C10-78.
DBGDRCR[0] Halt request bit
This enables the debugger to request a Debug state entry even if the processor is powered
down. Also, if the debugger makes this request before powering-down but the request
cannot be satisfied, for example because the processor is in Secure state but
(DBGEN AND SPIDEN) = 0, the request remains pending through power-down.
Note
The processor has to be powered up to respond to a pending DBGDRCR[0] Halt request or
External Debug request.
OS Lock Access Register
This enables the lock that the OS sets before saving the debug registers to remain set through
power-down. For details see OS Lock Access Register (DBGOSLAR) on page C10-75.
Device Power-down and Reset registers
These registers must be in the debug power domain because some of their functions are used
for debugging power-down events. See Device Power-down and Reset Control Register
(DBGPRCR), v7 Debug only on page C10-31, Device Power-down and Reset Status
Register (DBGPRSR), v7 Debug only on page C10-34.
Lock Access Register, if implemented
If implemented, this register must be in the debug power domain because it is used to enable
certain accesses by external debug interface, and this functionality is required when
debugging power-down events.
Identification registers and the DBGDIDR
The identification registers are at addresses 0xD00-0xDFC, and 0xFD0-0xFEC. For details of
these registers see Management registers, ARMv7 only on page C10-88.
Debugger operation only requires the above registers and bits to be in the debug power domain. However,
to rationalize the split between the debug and core power domains in the register map, ARMv7 requires an
implementation that supports debug over power-down to have all bits of the following registers in the debug
power domain:
DBGDIDR, DBGECR, and DBGDRCR
No error response is returned on read or write accesses when the core power domain is
powered down.
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