ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARMv4 and ARMv5 Differences
The ARM abort model
ARMv6 and ARMv7 use a Base Restored Abort Model (BRAM). However, in ARMv5 and ARMv4 it is
IMPLEMENTATION DEFINED whether this model, or a Base Updated Abort Model (BUAM) is used. These
two abort models are defined as:
Base Restored Abort Model
The base register of any valid load/store instruction that causes a memory system abort is
always restored to the value it had immediately before that instruction.
Base Updated Abort Model
After an abort, the base register of any valid load/store instruction that causes a memory
system abort is modified by the base register writeback, if any, of that instruction.
The implemented abort model applies uniformly across all instructions.
Exception entry
Entry to exceptions in ARMv4 and ARMv5 is generally as described in the sections:
Reset on page B1-48
Undefined Instruction exception on page B1-49
Supervisor Call (SVC) exception on page B1-52
Secure Monitor Call (SMC) exception on page B1-53
Prefetch Abort exception on page B1-54
Data Abort exception on page B1-55
IRQ exception on page B1-58
FIQ exception on page B1-60.
These ARMv7 descriptions are modified as follows:
pseudocode statements that set registers, bits and fields that do not exist in the ARMv4 or ARMv5
architecture variant are ignored
CPSR.T is set to 0, not to SCTLR.TE.
H.5.3 Execution environment support
In ARMv5TEJ, the JOSCR.CV bit is not changed on exception entry in any implementation of Jazelle.
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