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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Maximum <strong>and</strong> minimum<br />

// FPMax()<br />

// =======<br />

Application Level Programmers’ Model<br />

bits(N) FPMax(bits(N) op1, bits(N) op2, boolean fpscr_controlled)<br />

assert N == 32 || N == 64;<br />

fpscr_val = if fpscr_controlled then FPSCR else St<strong>and</strong>ardFPSCRValue();<br />

(type1,sign1,value1) = FPUnpack(op1, fpscr_val);<br />

(type2,sign2,value2) = FPUnpack(op2, fpscr_val);<br />

(done,result) = FPProcessNaNs(type1, type2, op1, op2, fpscr_val);<br />

if !done then<br />

if type1 == FPType_Zero && type2 == FPType_Zero && sign1 == NOT(sign2) then<br />

// Opposite-signed zeros produce +0.0<br />

result = FPZero(‘0’, N);<br />

else<br />

// All other cases can be evaluated on the values produced by FPUnpack()<br />

result = if value1 > value2 then op1 else op2;<br />

return result;<br />

// FPMin()<br />

// =======<br />

bits(N) FPMin(bits(N) op1, bits(N) op2, boolean fpscr_controlled)<br />

assert N == 32 || N == 64;<br />

fpscr_val = if fpscr_controlled then FPSCR else St<strong>and</strong>ardFPSCRValue();<br />

(type1,sign1,value1) = FPUnpack(op1, fpscr_val);<br />

(type2,sign2,value2) = FPUnpack(op2, fpscr_val);<br />

(done,result) = FPProcessNaNs(type1, type2, op1, op2, fpscr_val);<br />

if !done then<br />

if type1 == FPType_Zero && type2 == FPType_Zero && sign1 == NOT(sign2) then<br />

// Opposite-signed zeros produce -0.0<br />

result = FPZero(‘1’, N);<br />

else<br />

// All other cases can be evaluated on the values produced by FPUnpack()<br />

result = if value1 < value2 then op1 else op2;<br />

return result;<br />

Addition <strong>and</strong> subtraction<br />

// FPAdd()<br />

// =======<br />

bits(N) FPAdd(bits(N) op1, bits(N) op2, boolean fpscr_controlled)<br />

assert N == 32 || N == 64;<br />

fpscr_val = if fpscr_controlled then FPSCR else St<strong>and</strong>ardFPSCRValue();<br />

(type1,sign1,value1) = FPUnpack(op1, fpscr_val);<br />

(type2,sign2,value2) = FPUnpack(op2, fpscr_val);<br />

(done,result) = FPProcessNaNs(type1, type2, op1, op2, fpscr_val);<br />

if !done then<br />

inf1 = (type1 == FPType_Infinity); inf2 = (type2 == FPType_Infinity);<br />

zero1 = (type1 == FPType_Zero); zero2 = (type2 == FPType_Zero);<br />

if inf1 && inf2 && sign1 == NOT(sign2) then<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. A2-55

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