ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
Table B3-19 lists the CP15 c0 registers and shows where each register is described in full. The table does
not include the reserved and aliased registers that are shown in Figure B3-11 on page B3-79.
opc1 CRm opc2 Register and description
Note
Table B3-19 Index to CP15 c0 register descriptions
0 c0 0 c0, Main ID Register (MIDR) on page B3-81
1 c0, Cache Type Register (CTR) on page B3-83
2 c0, TCM Type Register (TCMTR) on page B3-85
3 c0, TLB Type Register (TLBTR) on page B3-86
5 c0, Multiprocessor Affinity Register (MPIDR) on page B3-87
4, 6, 7 c0, Main ID Register (MIDR) on page B3-81
c1 0, 1 CP15 c0, Processor Feature registers on page B5-4
2 c0, Debug Feature Register 0 (ID_DFR0) on page B5-6
3 c0, Auxiliary Feature Register 0 (ID_AFR0) on page B5-8
4-7 CP15 c0, Memory Model Feature registers on page B5-9
c2 0-5 CP15 c0, Instruction Set Attribute registers on page B5-19
1 c0 0 c0, Cache Size ID Registers (CCSIDR) on page B3-91
1 c0, Cache Level ID Register (CLIDR) on page B3-92
7 c0, Implementation defined Auxiliary ID Register (AIDR) on page B3-94
2 c0 0 c0, Cache Size Selection Register (CSSELR) on page B3-95
The CPUID scheme described in Chapter B5 The CPUID Identification Scheme includes information about
the implementation of the optional VFP and Advanced SIMD architecture extensions. See Advanced SIMD
and VFP extensions on page A2-20 for a summary of the implementation options for these features.
B3-80 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B