ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
0b10 Match on any store, Store-Exclusive or swap.
0b11 Match on any either type of access.
If an implementation supports watchpoint generation by:
a memory hint instruction, then that instruction is treated as generating a load access
a cache maintenance operation, then that operation is treated as generating a store
access.
Privileged mode control, bits [2:1]
This field enables watchpoint matching conditional on the mode of the processor. Possible
values of this field are:
0b00 Reserved.
0b01 Match privileged accesses.
0b10 Match unprivileged accesses.
0b11 Match all accesses.
Note
For all cases the match refers to the privilege of the access, not the mode of the
processor. For example, if the watchpoint is configured to match privileged accesses
only (0b01), and the processor executes an LDRT instruction in a privileged mode, the
watchpoint does not match.
Permitted values of this field are not identical to those for the DBGBCR. In the
DBGBCR only, in v7 Debug, the value 0b00 is permitted.
Watchpoint enable, bit [0]
This bit enables the WRP. The meaning of this bit is:
0 Watchpoint disabled
1 Watchpoint enabled.
A WRP never generates Watchpoint debug events when its DBGWCR is disabled.
The debug logic reset values of all bits of the DBGWCR is UNKNOWN.
Note
In v6 Debug and v6.1 Debug, the Watchpoint enable bit of the DBGWCR is set to 0 on a debug logic
reset, disabling the watchpoint.
In v7 Debug, a debugger must ensure that DBGWCR[0] has a defined state before it programs
DBGDSCR[15:14] to enable debug.
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