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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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<strong>ARM</strong>v6 Differences<br />

G.4 Instruction set support<br />

Two instruction sets are supported in <strong>ARM</strong>v6:<br />

the <strong>ARM</strong> instruction set<br />

the Thumb instruction set.<br />

<strong>ARM</strong>v6 floating-point support, known as VFPv2, is the same as that supported in <strong>ARM</strong>v5. The instructions<br />

use coprocessors 10 <strong>and</strong> 11 <strong>and</strong> are documented with all other instructions in Alphabetical list of<br />

instructions on page A8-14. The following VFP instructions are not supported in <strong>ARM</strong>v6. These<br />

instructions are introduced in <strong>ARM</strong>v7 (VFPv3):<br />

VMOV (immediate)<br />

VCVT (between floating-point <strong>and</strong> fixed-point).<br />

Note<br />

VFP instruction mnemonics traditionally started with an F. However this has been changed to a V<br />

prefix in the Unified Assembler Language introduced in <strong>ARM</strong>v6T2, <strong>and</strong> in many cases the rest of the<br />

mnemonic has been changed to be more compatible with other instructions mnemonics. This aligns<br />

the scalar floating-point support with the <strong>ARM</strong>v7 Advanced SIMD support, which shares some<br />

load/store <strong>and</strong> move operations to a common register file.<br />

The VFPv2 instructions are summarized in F* (former VFP instruction mnemonics) on page A8-100.<br />

This includes the two deprecated instructions in VFPv2 that do not have UAL mnemonics, the FLDMX<br />

<strong>and</strong> FSTMX instructions.<br />

<strong>ARM</strong>v6 introduces new instructions in addition to supporting all the <strong>ARM</strong> <strong>and</strong> Thumb instructions available<br />

in <strong>ARM</strong>v5TEJ. For more information, see Instruction set support on page AppxH-11, <strong>ARM</strong> instruction set<br />

support on page AppxG-11, <strong>and</strong> Thumb instruction set support on page AppxG-14.<br />

The <strong>ARM</strong> <strong>and</strong> Thumb instruction sets grew significantly in <strong>ARM</strong>v6 <strong>and</strong> <strong>ARM</strong>v6T2, compared with<br />

<strong>ARM</strong>v5TEJ, mainly because of:<br />

the development of <strong>ARM</strong>v6 SIMD<br />

the addition of many 32-bit Thumb instructions in <strong>ARM</strong>v6T2.<br />

<strong>ARM</strong>v6K adds some kernel support instructions. It also permits the use of the optional Security Extensions<br />

<strong>and</strong> the SMC instruction.<br />

<strong>ARM</strong>v7 extends the instruction sets as defined for <strong>ARM</strong>v6 <strong>and</strong> the <strong>ARM</strong>v6 architecture variants <strong>and</strong><br />

extensions as follows:<br />

the introduction of barrier instructions to the <strong>ARM</strong> <strong>and</strong> Thumb instruction sets<br />

the ThumbEE extension in <strong>ARM</strong>v7<br />

the new instructions added in VFPv3<br />

the Advanced SIMD extension in <strong>ARM</strong>v7.<br />

AppxG-10 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B

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