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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Assembler syntax<br />

VADDHN. , , <br />

where:<br />

Instruction Details<br />

See St<strong>and</strong>ard assembler syntax fields on page A8-7. An <strong>ARM</strong> VADDHN instruction<br />

must be unconditional.<br />

The data type for the elements of the oper<strong>and</strong>s. It must be one of:<br />

I16 size = 0b00<br />

I32 size = 0b01<br />

I64 size = 0b10.<br />

, , The destination vector, the first oper<strong>and</strong> vector, <strong>and</strong> the second oper<strong>and</strong> vector.<br />

Operation<br />

if ConditionPassed() then<br />

EncodingSpecificOperations(); CheckAdvSIMDEnabled();<br />

for e = 0 to elements-1<br />

result = Elem[Q[n>>1],e,2*esize] + Elem[Q[m>>1],e,2*esize];<br />

Elem[D[d],e,esize] = result;<br />

Exceptions<br />

Undefined Instruction.<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. A8-541

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