ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
VORR. {,} , # Encoded as Q = 1
VORR. {,} , #> Encoded as Q = 0
where:
Instruction Details
See Standard assembler syntax fields on page A8-7. An ARM VORR instruction must be
unconditional.
The data type used for . It can be either I16 or I32.
I8, I64, and F32 are also permitted, but the resulting syntax is a pseudo-instruction.
The destination vector for a quadword operation.
The destination vector for a doubleword operation.
A constant of the type specified by . This constant is replicated enough times to fill the
destination register. For example, VORR.I32 D0,#10 ORs 0x0000000A0000000A into D0.
For details of the range of constants available, and the encoding of and , see One register and a
modified immediate value on page A7-21.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
for r = 0 to regs-1
D[d+r] = D[d+r] OR imm64;
Exceptions
Undefined Instruction.
Pseudo-instructions
VORN can be used, with a range of constants that are the bitwise inverse of the available constants for VORR.
This is assembled as the equivalent VORR instruction. Disassembly produces the VORR form.
One register and a modified immediate value on page A7-21 describes pseudo-instructions with a
combination of and that is not supported by hardware, but that generates the same destination
register value as a different combination that is supported by hardware.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-679