ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Accessing the MIDR
Virtual Memory System Architecture (VMSA)
To access the MIDR you read the CP15 registers with set to 0, set to c0, set to c0, and
set to 0. For example:
MRC p15,0,,c0,c0,0 ; Read CP15 Main ID Register
B3.12.8 c0, Cache Type Register (CTR)
The Cache Type Register, CTR, provides information about the architecture of the caches.
The CTR is:
a 32-bit read-only register
accessible only in privileged modes
when the Security Extensions are implemented, a Common register.
The format of the CTR is changed in ARMv7. The new format of the register is indicated by Bit [31:29]
being set to 0b100. For details of the format of the Cache Type Register in versions of the ARM architecture
before ARMv7 see c0, Cache Type Register (CTR) on page AppxH-35.
In ARMv7, the format of the CTR is:
31 29 28 27 24 23 20 19 16 15 14 13 4 3 0
1 0 0 0 CWG ERG DminLine L1Ip 0 0 0 0 0 0 0 0 0 0 IminLine
Bits [31:29] Set to 0b100 for the ARMv7 register format. Set to 0b000 for the format used in ARMv6
and earlier.
Bit [28] RAZ.
CWG, bits [27:24]
Cache Writeback Granule. Log2 of the number of words of the maximum size of memory
that can be overwritten as a result of the eviction of a cache entry that has had a memory
location in it modified.
A value of 0b0000 indicates that the CTR does not provide Cache Writeback Granule
information and either:
the architectural maximum of 512 words (2Kbytes) must be assumed
the Cache Writeback Granule can be determined from maximum cache line size
encoded in the Cache Size ID Registers.
Values greater than 0b1001 are reserved.
ERG, bits [27:24]
Exclusives Reservation Granule. Log2 of the number of words of the maximum size of the
reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive
instructions. For more information, see Tagging and the size of the tagged memory block on
page A3-20.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B3-83