ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
The four options are:
Section A 1MB memory region, described by a first-level translation table descriptor with bits
[18,1:0] == 0b010.
See Translation flow for a Section on page B3-17.
Supersection A 16MB memory region, described by a first-level translation table entry with bits
[18,1:0] == 0b110.
See Translation flow for a Supersection on page B3-18.
Small page A 4KB memory region, described by:
a first-level translation table entry with bits [1:0] == 0b01, giving a second-level Page
table address.
a second-level descriptor with bit [1] == 1.
See Translation flow for a Small page on page B3-19.
Large page A 64KB memory region, described by:
a first-level translation table entry with bits [1:0] == 0b01, giving a second-level Page
table address.
a second-level descriptor with bits [1:0] == 0b01.
See Translation flow for a Large page on page B3-20.
B3-16 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B