ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
where:
Must be either MLA (op = 0) or MLS (op = 1).
Instruction Details
V. , , Encoding T1 / A1, Q = 1
V. , , Encoding T1 / A1, Q = 0
VL. , , Encoding T2 / A2
See Standard assembler syntax fields on page A8-7. An ARM Advanced SIMD
VMLA, VMLAL, VMLS, or VMLSL instruction must be unconditional.
The data type for the elements of the operands. It must be one of:
S Optional in encoding T1 / A1. U = 0 in encoding T2 / A2.
U Optional in encoding T1 / A1. U = 1 in encoding T2 / A2.
I Available only in encoding T1 / A1.
The data size for the elements of the operands. It must be one of:
8 encoded as size = 0b00
16 encoded as size = 0b01
32 encoded as size = 0b10.
, , The destination vector and the operand vectors, for a quadword operation.
, , The destination vector and the operand vectors, for a doubleword operation.
, , The destination vector and the operand vectors, for a long operation.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
for r = 0 to regs-1
for e = 0 to elements-1
product = Int(Elem[D[n+r],e,esize],unsigned) * Int(Elem[D[m+r],e,esize],unsigned);
addend = if add then product else -product;
if long_destination then
Elem[Q[d>>1],e,2*esize] = Elem[Q[d>>1],e,2*esize] + addend;
else
Elem[D[d+r],e,esize] = Elem[D[d+r],e,esize] + addend;
Exceptions
Undefined Instruction.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-635