ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The System Level Programmers’ Model
Aborts, exceptions, and checks
Aborts and exceptions are unchanged in ThumbEE. A null check takes priority over an abort or watchpoint
on the same memory access. For more information, see Null checking on page A9-3.
The IT state bits in the CPSR are always cleared on entry to a NullCheck or IndexCheck handler. For more
information, see IT block and check handlers on page A9-5.
B1.9.2 Jazelle direct bytecode execution
In Jazelle state the processor executes bytecode programs, as described in Jazelle state on page A2-74.
The processor instruction set state is indicated by the CPSR.J and CPSR.T bits, see Program Status
Registers (PSRs) on page B1-14. (J,T) == 0b10 when the processor is in Jazelle state. For more information
about entering and leaving Jazelle state see Jazelle state on page B1-81.
Extension of the PC to 32 bits
To enable the PC to point to an arbitrary bytecode instruction, in a non-trivial Jazelle implementation all 32
bits of the PC are defined. In the PC, bit [0] always reads as zero when in ARM, Thumb, or ThumbEE state.
The existence of bit [0] in the PC is only visible in ARM, Thumb, or ThumbEE states when an exception
occurs in Jazelle state and the exception return address is odd-byte aligned.
The main architectural implication of this is that an exception handler must ensure that it restores all 32 bits
of the PC. The recommended ways of handling exception returns behave correctly.
Exception handling in the Jazelle extension
Exceptions on page B1-30 describes how exception entry occurs if an exception occurs while the processor
is executing in Jazelle state. This section gives more information about how exceptions in Jazelle state are
taken and handled.
Interrupts and Fast interrupts, IRQ and FIQ
To enable the standard mechanism for handling interrupts to work correctly, a Jazelle hardware
implementation must ensure that one of the following applies at the point where execution of a bytecode
instruction might be interrupted by an IRQ or FIQ:
Execution has reached a bytecode instruction boundary. That is:
— all operations required to implement one bytecode instruction have completed
— no operations required to implement the next bytecode instruction has completed.
The LR value on entry to the interrupt handler must be (address of the next bytecode instruction) + 4.
The sequence of operations performed from the start of execution of the current bytecode instruction,
up to the point where the interrupt occurs, is idempotent. This means that the sequence can be
repeated from its start without changing the overall result of executing the bytecode instruction.
B1-74 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B