ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Translation flow for a Section
Virtual Memory System Architecture (VMSA)
Figure B3-4 shows the virtual to physical addresses translation for a Section. For details of the access
control fields in the first-level descriptor see the Section entry in Table B3-1 on page B3-8.
Translation Table
Base Register
MVA
PA[31:0] of
first-level descriptor
PA[39:32] = 0x00
First-level
Section descriptor
31 14-N 13-N
Translation base SBZ
31 32-N 31-N
20 19
Table index
31 14-N 13-N 2 1
Translation base Table index
First-level
read
Figure B3-4 Section address translation
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B3-17
0
0
0 0
31 20 19
Section
base address
31 20 19
PA[31:0]
PA[39:32] = 0x00
Section
base address
For a translation based on TTBR0, N is the value of TTBCR.N
For a translation based on TTBR1, N is 0
‡ This field is absent if N==0
‡
Section index
Access control fields
Section index
2 1
0
0
1 0
0