ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Application Level Memory Model
For applications of the ARMv7-R profile, there are some legacy code situations where the arrangement of
the bytes in the object files cannot be adjusted by the linker. For these object files to be used by an ARMv7-R
processor the byte order of the instructions must be reversed by the processor at runtime. Therefore, the
ARMv7-R profile permits configuration of the instruction endianness.
Instruction endianness static configuration, ARMv7-R only
To provide support for legacy big-endian object code, the ARMv7-R profile supports optional byte order
reversal hardware as a static option from reset. The ARMv7-R profile includes a read-only bit in the CP15
Control Register, SCTLR.IE, bit [31]. For more information, see c1, System Control Register (SCTLR) on
page B4-45.
A3.3.3 Element size and endianness
The effect of the endianness mapping on data transfers depends on the size of the data element or elements
transferred by the load/store instructions. Table A3-5 lists the element sizes of all the load/store instructions,
for all instruction sets.
Instructions Element size
LDRB, LDREXB, LDRBT, LDRSB, LDRSBT, STRB, STREXB, STRBT, SWPB, TBB Byte
LDRH, LDREXH, LDRHT, LDRSH, LDRSHT, STRH, STREXH, STRHT, TBH Halfword
LDR, LDRT, LDREX, STR, STRT, STREX Word
LDRD, LDREXD, STRD, STREXD Word
All forms of LDM, PUSH, POP, RFE, SRS, all forms of STM, SWP Word
LDC, LDC2, STC, STC2, VLDM, VLDR, VSTM, VSTR Word
Table A3-5 Element size of load/store instructions
VLD1, VLD2, VLD3, VLD4, VST1, VST2, VST3, VST4 Element size of the Advanced SIMD access
A3.3.4 Instructions to reverse bytes in a general-purpose register
An application or device driver might have to interface to memory-mapped peripheral registers or shared
memory structures that are not the same endianness as the internal data structures. Similarly, the endianness
of the operating system might not match that of the peripheral registers or shared memory. In these cases,
the processor requires an efficient method to transform explicitly the endianness of the data.
In ARMv7, the ARM and Thumb instruction sets provide this functionality. There are instructions to:
Reverse word (four bytes) register, for transforming big and little-endian 32-bit representations. See
REV on page A8-272.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A3-9