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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Instruction Details<br />

A8.6.378 VRSQRTE<br />

Vector Reciprocal Square Root Estimate finds an approximate reciprocal square root of each element in a<br />

vector, <strong>and</strong> places the results in a second vector.<br />

The oper<strong>and</strong> <strong>and</strong> result elements are the same type, <strong>and</strong> can be 32-bit floating-point numbers, or 32-bit<br />

unsigned integers.<br />

For details of the operation performed by this instruction see Reciprocal square root on page A2-61.<br />

Encoding T1 / A1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)<br />

VRSQRTE. , <br />

VRSQRTE. , <br />

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

1 1 1 1 1 1 1 1 1 D 1 1 size 1 1 Vd 0 1 0 F 1 Q M 0 Vm<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

1 1 1 1 0 0 1 1 1 D 1 1 size 1 1 Vd 0 1 0 F 1 Q M 0 Vm<br />

if Q == ‘1’ && (Vd == ‘1’ || Vm == ‘1’) then UNDEFINED;<br />

if size != ‘10’ then UNDEFINED;<br />

floating_point = (F == ‘1’); esize = 32; elements = 2;<br />

d = UInt(D:Vd); m = UInt(M:Vm); regs = if Q == ‘0’ then 1 else 2;<br />

A8-742 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B

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