ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Advanced SIMD and VFP Instruction Encoding
A7.7 Advanced SIMD element or structure load/store instructions
The allocation of encodings in this space is shown in:
Table A7-20 if L == 0, store instructions
Table A7-21 on page A7-28 if L == 1, load instructions.
Other encodings in this space are UNDEFINED.
Thumb encoding
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 1 A L 0 B
ARM encoding
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 1 0 0 A L 0 B
The variable bits are in identical locations in the two encodings, after adjusting for the fact that the ARM
encoding is held in memory as a single word and the Thumb encoding is held as two consecutive halfwords.
The ARM instructions can only executed unconditionally. The Thumb instructions can be executed
conditionally by using the IT instruction. For details see IT on page A8-104.
A B Instruction See
0 0010
011x
1010
0011
100x
Table A7-20 Element and structure store instructions (L == 0)
Vector Store VST1 (multiple single elements) on page A8-768
Vector Store VST2 (multiple 2-element structures) on page A8-772
010x Vector Store VST3 (multiple 3-element structures) on page A8-776
000x Vector Store VST4 (multiple 4-element structures) on page A8-780
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A7-27