ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
B3.12.29 CP15 c6, Fault Address registers
There are two Fault Address registers, in CP15 c6, as shown in Figure B3-15 on page B3-120s. The two
Fault Address registers complement the Fault Status registers, and are shown in Table B3-31.
Register name Description
Data Fault Address Register (DFAR) c6, Data Fault Address Register (DFAR)
Note
Before ARMv7:
The DFAR was called the Fault Address Register (FAR).
The Watchpoint Fault Address Register (DBGWFAR) was implemented in CP15 c6, with =1.
From ARMv7, the DBGWFAR is only implemented as a CP14 debug register, see Watchpoint Fault
Address Register (DBGWFAR) on page C10-28.
Fault information is returned using the fault address registers and the fault status registers described in CP15
c5, Fault status registers on page B3-121. For details of how these registers are used, and when the value in
the IFAR is valid, see Fault Status and Fault Address registers in a VMSA implementation on page B3-48.
c6, Data Fault Address Register (DFAR)
The Data Fault Address Register, DFAR, holds the MVA of the faulting address that caused a synchronous
Data Abort exception.
The DFAR is:
a 32-bit read/write register
accessible only in privileged modes
when the Security Extensions are implemented, a Banked register.
The format of the DFAR is:
For information about using the DFAR, and when the value in the DFAR is valid, see Fault Status and Fault
Address registers in a VMSA implementation on page B3-48.
A debugger can write to the DFAR to restore its value.
Table B3-31 Fault Address registers
Instruction Fault Address Register (IFAR) c6, Instruction Fault Address Register (IFAR) on page B3-125
31 0
MVA of faulting address of synchronous Data Abort exception
B3-124 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B