ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The CPUID Identification Scheme
Revision, bits [3:0]
B5.3.2 Media and VFP Feature registers
An IMPLEMENTATION DEFINED revision number for the floating-point implementation.
The Media and VFP Feature registers describe the features provided by the Advanced SIMD and VFP
extensions, when an implementation includes either or both of these extensions. For details of the
implementation options for these extensions see Advanced SIMD and VFP extensions on page A2-20.
In VFPv2, it is IMPLEMENTATION DEFINED whether the Media and VFP Feature registers are implemented.
Note
Often, the complete implementation of a VFP architecture uses support code to provide some VFP
functionality. In such an implementation, only the support code can provide full details of the supported
features. In this case the Media and VFP Feature registers are not used directly.
The Media and VFP Feature registers are described in:
Media and VFP Feature Register 0 (MVFR0)
Media and VFP Feature Register 1 (MVFR1) on page B5-38.
Media and VFP Feature Register 0 (MVFR0)
The format of the MVFR0 register is:
31 28 27 24 23 20 19
16 15 12 11 8 7 4 3 0
VFP
rounding
modes
Short
vectors
VFP rounding modes, bits [31:28]
Square
root
Divide
VFP
exception
trapping
Double-
precision
Single-
precision
Indicates the rounding modes supported by the VFP floating-point hardware. Permitted
values are:
0b0000 Only Round to Nearest mode supported, except that Round towards Zero mode
is supported for VCVT instructions that always use that rounding mode
regardless of the FPSCR setting.
0b0001 All rounding modes supported.
Short vectors, bits [27:24]
Indicates the hardware support for VFP short vectors. Permitted values are:
0b0000 Not supported.
0b0001 Short vector operation supported.
A_SIMD
registers
B5-36 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B