ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Instruction Set Encoding
A5.2.12 Miscellaneous instructions
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 0 0 0 1 0 op 0 op1 0 op2
Table A5-14 shows the allocation of encodings in this space.
Other encodings in this space are UNDEFINED.
Table A5-14 Miscellaneous instructions
op2 op op1 Instruction or instruction class See Variant
000 x0 xxxx Move Special Register to Register MRS on page A8-206
MRS on page B6-10
01 xx00 Move to Special Register, application level MSR (register) on page A8-210 All
xx01
xx1x
Move to Special Register, system level MSR (register) on page B6-14 All
11 - Move to Special Register, system level MSR (register) on page B6-14 All
001 01 - Branch and Exchange BX on page A8-62 v4T
11 - Count Leading Zeros CLZ on page A8-72 v6
010 01 - Branch and Exchange Jazelle BXJ on page A8-64 v5TEJ
011 01 - Branch with Link and Exchange BLX (register) on page A8-60 v5T
101 - - Saturating addition and subtraction Saturating addition and
subtraction on page A5-13
111 01 - Breakpoint BKPT on page A8-56 v5T
11 - Secure Monitor Call SMC (previously SMI) on
page B6-18
A5-18 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B
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Security
Extensions