ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

interrupt and asynchronous abort disable bits.
The System Level Programmers’ Model
The non-APSR bits of the CPSR have defined reset values. These are shown in the TakeReset() pseudocode
function, see Reset on page B1-48.
Writes to the CPSR have side-effects on various aspects of processor operation. All of these side-effects,
except for those on memory accesses caused by fetching instructions, are synchronous to the CPSR write.
This means they are guaranteed not to be visible to earlier instructions in the execution stream, and they are
guaranteed to be visible to later instructions in the execution stream.
Fetching an instruction causes an instruction fetch memory access. In addition, in a Virtual Memory System
Architecture (VMSA) implementation, fetching an instruction can cause a translation table walk. The
privilege of these memory accesses can be affected by changes to the mode field of the CPSR. Also, if the
Security Extensions are implemented the virtual memory space of these accesses can be affected by changes
to the mode field. Those mode changes take effect on the memory accesses as follows:
A mode change by an exception entry is synchronous to the exception entry. This applies to all
exception entries, including the exception entry for a synchronous exception generated directly by an
instruction.
A mode change by an exception return instruction is synchronous to the instruction.
A mode change by an instruction other than an exception return and that is not the result of a
synchronous exception generated directly by the instruction. Such a mode change can be the result
of a CPS or MSR instructions, and:
— is guaranteed not to be visible to memory accesses caused by fetching earlier instructions in
the execution stream
— is guaranteed to be visible to memory accesses caused by fetching instructions after the next
exception entry, exception return instruction, or ISB instruction in the execution stream
— might or might not affect memory accesses caused by fetching instructions between the mode
change instruction and the point where mode changes are guaranteed to be visible.
See Exception return on page B1-38 for the definition of exception return instructions.
The Saved Program Status Registers (SPSRs)
The purpose of an SPSR is to record the pre-exception value of the CPSR. When taking an exception, the
processor copies the CPSR to the SPSR of the exception mode it is about to enter. Saving this value means
the exception handler can:
on exception return, restore the CPSR to the value it had when the exception was taken
examine the value the CPSR had when the exception was taken, for example to determine the
instruction set state in which the instruction that caused an Undefined Instruction exception was
executed.
The SPSRs do not have defined reset values.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B1-15