ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
USAT , #, {,}
where:
See Standard assembler syntax fields on page A8-7.
The destination register.
The bit position for saturation, in the range 0 to 31.
The register that contains the value to be saturated.
Instruction Details
The optional shift, encoded in the sh bit and five bits in imm3:imm2 for encoding T1 and
imm5 for encoding A1. It must be one of:
omitted No shift. Encoded as sh = 0, five bits = 0b00000
LSL # Left shift by bits, with in the range 1-31.
Encoded as sh = 0, five bits = .
ASR # Arithmetic right shift by bits, with in the range 1-31.
Encoded as sh = 1, five bits = .
ASR #32 Arithmetic right shift by 32 bits, permitted only for encoding A1.
Encoded as sh = 1, imm5 = 0b00000.
Operation
Note
An assembler can permit ASR #0 or LSL #0 to mean the same thing as omitting the shift, but
this is not standard UAL and must not be used for disassembly.
if ConditionPassed() then
EncodingSpecificOperations();
operand = Shift(R[n], shift_t, shift_n, APSR.C); // APSR.C ignored
(result, sat) = UnsignedSatQ(SInt(operand), saturate_to);
R[d] = ZeroExtend(result, 32);
if sat then
APSR.Q = ‘1’;
Exceptions
None.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-505