ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
To reduce the software overhead of TLB maintenance, the VMSA distinguishes between Global pages and
Process specific pages. The Address Space Identifier (ASID) identifies pages associated with a specific
process and provides a mechanism for changing process specific tables without having to perform
maintenance on the TLB structures.
System Control coprocessor (CP15) registers control the VMSA, including defining the location of the
translation tables. They include registers that contain memory fault status and address information. See
CP15 registers for a VMSA implementation on page B3-64. When the Security Extensions are implemented,
many of the CP15 registers are banked between the Secure and Non-secure security states. This means
separate system control software can be used in the different security states.
VMSAv7 supports physical addresses of up to 40 bits, though implementations are permitted to support only
32 bits of physical address. Where implementations support more than 32 bits of physical address,
generating physical addresses with PA[39:32] != 0b00000000 requires the use of Supersections, see
Translation tables on page B3-7.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B3-3