ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Glossary
Memory coherency
Is the problem of ensuring that when a memory location is read (either by a data read or an instruction fetch),
the value actually obtained is always the value that was most recently written to the location. This can be
difficult when there are multiple possible physical locations, such as main memory, a write buffer and/or
cache(s).
Memory Management Unit (MMU)
Provides detailed control of a memory system. Most of the control is provided via translation tables held in
memory.
Memory-mapped I/O
Uses special memory addresses that supply I/O functions when they are loaded from or stored to.
Memory Protection Unit (MPU)
Is a hardware unit whose registers provide simple control of a limited number of protection regions in
memory.
Mixed-endian
A processor supports mixed-endian memory accesses if accesses to big-endian data and little-endian data
can be freely intermixed, with only small performance and code size penalties for doing so.
Modified Virtual Address (MVA)
Is the address produced by the FCSE that is sent to the rest of the memory system to be used in place of the
normal virtual address. From ARMv6, use of the FCSE is deprecated, and the FCSE is optional in ARMv7.
When the FCSE is absent or disabled the MVA and the Virtual Address (VA) have the same value.
MMU See Memory Management Unit.
MPU See Memory Protection Unit.
Multi-copy atomicity
Is the form of atomicity described in Multi-copy atomicity on page A3-28.
See also Atomicity, Single-copy atomicity.
MVA See Modified Virtual Address.
NaN NaNs are special floating-point values that can be used when neither a numeric value nor an infinity is
appropriate. NaNs can be quiet NaNs that propagate through most floating-point operations, or signaling
NaNs that cause Invalid Operation floating-point exceptions when used. For details, see the IEEE 754
standard.
Observer
A processor or mechanism in the system, such as a peripheral device, that can generate reads from or writes
to memory.
Offset addressing
Means that the memory address is formed by adding or subtracting an offset to or from the base register
value.
PA See Physical address.
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