ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

c0, Instruction Set Attribute Register 3 (ID_ISAR3)
The format of the ID_ISAR3 is:
ThumbEE_extn_instrs, bits [31:28]
The CPUID Identification Scheme
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
ThumbEE_
extn_instrs
TrueNOP
_instrs
ThumbCopy
_instrs
TabBranch
_instrs
SynchPrim
_instrs
SVC
_instrs
SIMD
_instrs
Saturate
_instrs
Indicates the supported Thumb Execution Environment (ThumbEE) extension instructions.
Permitted values are:
0b0000 None supported.
0b0001 Adds support for the ENTERX and LEAVEX instructions, and modifies the load
behavior to include null checking.
Note
This field can only have a value other than 0b0000 when the PFR0 register State3 field has
a value of 0b0001, see c0, Processor Feature Register 0 (ID_PFR0) on page B5-4.
TrueNOP_instrs, bits [27:24]
Indicates the support for True NOP instructions. Permitted values are:
0b0000 None supported. This means there are no NOP instructions that do not have any
register dependencies.
0b0001 Adds true NOP instructions in both the Thumb and ARM instruction sets. Also
permits additional NOP-compatible hints.
ThumbCopy_instrs, bits [23:20]
Indicates the supported Thumb non flag-setting MOV instructions. Permitted values are:
0b0000 Not supported. This means that in the Thumb instruction set, encoding T1 of the
MOV (register) instruction does not support a copy from a low register to a low
register.
0b0001 Adds support for Thumb instruction set encoding T1 of the MOV (register)
instruction, copying from a low register to a low register.
TabBranch_instrs, bits [19:16]
Indicates the supported Table Branch instructions in the Thumb instruction set. Permitted
values are:
0b0000 None supported.
0b0001 Adds support for the TBB and TBH instructions.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B5-29