ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Protected Memory System Architecture (PMSA)
Data formats for the cache and branch predictor operations
Table B4-19 on page B4-69 shows three possibilities for the data in the register Rt specified by the MCR
instruction. These are described in the following subsections:
Ignored
Address
Set/way on page B4-71
Ignored
The value in the register specified by the MCR instruction is ignored. You do not have to write a value to the
register before issuing the MCR instruction.
Address
Table B4-19 CP15 c7 cache and branch predictor maintenance operations (continued)
CRm opc2 Mnemonic Function a Rt data
c5 7 BPIMVA Invalidate address from branch predictor array in the inner
shareable domain. d
Address
c6 1 DCIMVAC Invalidate data or unified cache line by address to PoU. d Address
c6 2 DCISW Invalidate data or unified cache line by set/way. Set/way
c10 1 DCCMVAC Clean data or unified cache line by address to PoC. d Address
c10 2 DCCSW Clean data or unified cache line by set/way. Set/way
c11 1 DCCMVAU Clean data or unified cache line by address to PoU. d Address
c14 1 DCCIMVAC Clean and invalidate data or unified cache line by address to PoC. d Address
c14 2 DCCISW Clean and invalidate data or unified cache line by set/way. Set/way
a. Address, point of coherency (PoC) and point of unification (PoU) are described in Terms used in describing cache
operations on page B2-10.
b. Only applies to separate instruction caches, does not apply to unified caches.
c. Only applies to separate instruction caches, does not apply to unified caches.
d. In general descriptions of the cache operations, these functions are described as operating by MVA
(Modified Virtual Address). In a PMSA implementation the MVA and the PA have the same value, and so
the functions operate using a physical address in the memory map.
In general descriptions of the maintenance operations, operations that require a memory address are
described as operating by MVA. For more information, see Terms used in describing cache operations on
page B2-10. In a PMSA implementation, these operations require the physical address in the memory map.
When the data is stated to be an address, it does not have to be cache line aligned.
B4-70 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B