ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Register In a Description, see
ICR, pre-ARMv6 c2, Memory Region Cacheability Registers (DCR and ICR) on
page AppxH-44
ID_AFR0 c0, Auxiliary Feature Register 0 (ID_AFR0) on page B5-8
ID_DFR0 c0, Debug Feature Register 0 (ID_DFR0) on page B5-6
Register Index
ID_ISAR0 c0, Instruction Set Attribute Register 0 (ID_ISAR0) on page B5-24
ID_ISAR1 c0, Instruction Set Attribute Register 1 (ID_ISAR1) on page B5-25
ID_ISAR2 c0, Instruction Set Attribute Register 2 (ID_ISAR2) on page B5-27
ID_ISAR3 c0, Instruction Set Attribute Register 3 (ID_ISAR3) on page B5-29
ID_ISAR4 c0, Instruction Set Attribute Register 4 (ID_ISAR4) on page B5-31
ID_ISAR5 c0, Instruction Set Attribute Register 5 (ID_ISAR5) on page B5-33
ID_MMFR0 c0, Memory Model Feature Register 0 (ID_MMFR0) on page B5-9
ID_MMFR1 c0, Memory Model Feature Register 1 (ID_MMFR1) on page B5-11
ID_MMFR2 c0, Memory Model Feature Register 2 (ID_MMFR2) on page B5-14
ID_MMFR3 c0, Memory Model Feature Register 3 (ID_MMFR3) on page B5-17
ID_PFR0 c0, Processor Feature Register 0 (ID_PFR0) on page B5-4
ID_PFR1 c0, Processor Feature Register 1 (ID_PFR1) on page B5-5
ID, Debug Debug ID Register (DBGDIDR) on page C10-3
IEAPR, pre-ARMv6 c5, Memory Region Extended Access Permissions Registers (DEAPR
and IEAPR) on page AppxH-46
IFAR PMSA c6, Instruction Fault Address Register (IFAR) on page B4-58
VMSA c6, Instruction Fault Address Register (IFAR) on page B3-125
IFSR PMSA c5, Instruction Fault Status Register (IFSR) on page B4-56
VMSA c5, Instruction Fault Status Register (IFSR) on page B3-122
IMRR0-IMRR7, pre-ARMv6 c6, Memory Region registers (DMRR0-DMRR7 and IMRR0-IMRR7) on
page AppxH-47
Instruction Cache Lockdown,
pre-ARMv7
c9, cache lockdown support on page AppxH-52
Table K-1 Register index (continued)
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxK-13