ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
VSUBHN. , ,
where:
Instruction Details
See Standard assembler syntax fields on page A8-7. An ARM VSUBHN instruction
must be unconditional.
The data type for the elements of the operands. It must be one of:
I16 size = 0b00
I32 size = 0b01
I64 size = 0b10.
, , The destination vector, the first operand vector, and the second operand vector.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
for e = 0 to elements-1
result = Elem[Q[n>>1],e,2*esize] - Elem[Q[m>>1],e,2*esize];
Elem[D[d],e,esize] = result;
Exceptions
Undefined Instruction.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-793