ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The System Level Programmers’ Model
The security state is largely independent of the processor mode. The only exception
to this independence of security state and processor mode is Monitor mode. Monitor
mode exists only in the Secure state, and supports transitions between Secure and
Non-secure state.
Some system control resources are only accessible from the Secure state.
For more information, see The Security Extensions on page B1-25.
Note
In some documentation, the Secure state is described as the Secure world, and the
Non-secure state is described as the Non-secure world.
When the Security Extensions are not implemented, the ARM architecture provides
only a single security state.
Debug state Debug state refers to the processor being halted for debug purposes, because a debug event
has occurred when the processor is configured to Halting debug-mode. See Invasive debug
on page C1-3.
When the processor is not in Debug state it is in Non-debug state.
Except where explicitly stated otherwise, parts A and B of this manual describe processor
behavior and instruction execution in Non-debug state. Chapter C5 Debug State describes
the differences in Debug state.
B1.2.2 Exceptions
An exception is a condition that changes the normal flow of control in a program. The change of flow
switches execution to an exception handler, and the state of the system at the point where the exception
occurred is presented to the exception handler. A key component of the state presented to the handler is the
return address, that indicates the point in the instruction stream where the exception was taken.
The ARM architecture provides a number of different exceptions as described in Exceptions on page B1-30.
Terminology for describing exceptions
In this manual, a number of terms have specific meanings when used to describe exceptions:
An exception is generated in one of the following ways:
— Directly as a result of the execution or attempted execution of the instruction stream. For
example, an exception is generated as a result of an UNDEFINED instruction.
— Less directly, as a result of something in the state of the system. For example, an exception is
generated as a result of an interrupt signaled by a peripheral.
An exception is taken by a processor at the point where it causes a change to the normal flow of
control in the program.
B1-4 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B