ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
If the external interface input DBGEN is LOW, the MDBGen bit reads as 0. The
programmed value is masked until DBGEN is taken HIGH. When DBGEN goes HIGH, the
value read and the behavior of the processor correspond to the programmed value.
Note
If Halting debug-mode is enabled, by setting the HDBGen bit to 1, then the Monitor
debug-mode setting is disabled regardless of the setting of the MDBGen bit.
It is the programmed value of the MDBGen bit, not the value returned by reads of the
DBGDSCR, that is saved by the OS Save and Restore Register in a power-down
sequence. For more information, see The OS Save and Restore mechanism on
page C6-8.
HDBGen, bit [14]
Halting debug-mode enable bit. The possible values of this bit are:
0 Halting debug-mode disabled
1 Halting debug-mode enabled.
If the external interface input DBGEN is LOW, the HDBGen bit reads as 0. The
programmed value is masked until DBGEN is taken HIGH. When DBGEN goes HIGH, the
value read and the behavior of the processor correspond to the programmed value.
Note
It is the programmed value of the HDBGen bit, not the value returned by reads of the
DBGDSCR, that is saved by the OS Save and Restore Register in a power-down sequence.
For more information, see The OS Save and Restore mechanism on page C6-8.
ITRen, bit [13]
Execute ARM instruction enable bit. This bit enables the execution of ARM instructions
through the DBGITR, see Instruction Transfer Register (DBGITR) on page C10-46. The
possible values of this bit are:
0 ITR mechanism disabled
1 The ITR mechanism for forcing the processor to execute instructions in Debug
state via the external debug interface is enabled.
Setting this bit to 1 when the processor is in Non-debug state causes UNPREDICTABLE
behavior. The effect of writing to DBGITR when this bit is set to 0 is UNPREDICTABLE.
The implementation of this bit can depend on the Debug architecture version:
ARMv6 If the external debug interface does not have a mechanism for forcing the
processor to execute instructions in Debug state via the external debug interface,
this bit is RAZ/WI.
v7 Debug This bit, and the DBGITR, are required.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-15