ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
V.8 , ,
where:
Specifies the operation. It must be one of:
TBL encoded as op = 0
TBX encoded as op = 1
Instruction Details
See Standard assembler syntax fields on page A8-7. An ARM VTBL or VTBX instruction must
be unconditional.
The destination vector.
The vectors containing the table. It must be one of:
{} encoded as len = 0b00
{,} encoded as len = 0b01
{,,} encoded as len = 0b10
{,,,}
The index vector.
Operation
encoded as len = 0b11
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
// Create 256-bit = 32-byte table variable, with zeros in entries that will not be used.
table3 = if length == 4 then D[n+3] else Zeros(64);
table2 = if length >= 3 then D[n+2] else Zeros(64);
table1 = if length >= 2 then D[n+1] else Zeros(64);
table = table3 : table2 : table1 : D[n];
for i = 0 to 7
index = UInt(Elem[D[m],i,8]);
if index < 8*length then
Elem[D[d],i,8] = Elem[table,index,8];
else
if is_vtbl then
Elem[D[d],i,8] = Zeros(8);
// else Elem[D[d],i,8] unchanged
Exceptions
Undefined Instruction.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-799