ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

B3.3 Translation tables
Virtual Memory System Architecture (VMSA)
The MMU supports memory accesses based on memory sections or pages:
Supersections Consist of 16MB blocks of memory. Support for Supersections is optional.
Sections Consist of 1MB blocks of memory.
Large pages Consist of 64KB blocks of memory.
Small pages Consist of 4KB blocks of memory.
Support for Supersections, Sections and Large pages enables a large region of memory to be mapped using
only a single entry in the TLB.
The translation tables held in memory have two levels:
First-level table
Holds first-level descriptors that contain the base address and
translation properties for Sections and Supersections
translation properties and pointers to a second level table for Large pages and Small
pages
Second-level tables
Hold second-level descriptors, each containing the base address and translation properties
for a Small pages or a Large page. Second-level tables are also referred to as Page tables.
The translation tables are described in the following sections:
Translation table entry formats
Translation table base registers on page B3-11
Translation table walks on page B3-13
Changing translation table attributes on page B3-21
The access flag on page B3-21.
B3.3.1 Translation table entry formats
The formats of the first-level and second-level translation table descriptor entries in the translation tables are
described in:
First-level descriptors on page B3-8
Second-level descriptors on page B3-10.
For more information about second-level translation tables see Additional requirements for translation
tables on page B3-11.
Note
In previous versions of the ARM Architecture Reference Manual and in some other documentation, the
AP[2] bit in the translation table entries is described as the APX bit.
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