ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Writing to the PC
In ARMv7, instruction writes to the PC are handled as follows:
The System Level Programmers’ Model
Exception return instructions write both the PC and the CPSR. The value written to the CPSR
determines the new instruction set state, and the value written to the PC determines the address that
is branched to. For full details, including which instructions are exception return instructions and how
incorrectly aligned PC values are handled, see Exception return on page B1-38.
The following two 16-bit Thumb instruction encodings remain in Thumb state and branch to a value
written to the PC:
— encoding T2 of ADD (register) on page A8-24
— encoding T1 of MOV (register) on page A8-196.
The value written to the PC is forced to be halfword-aligned by ignoring its least significant bit,
instead treating that bit as being 0.
The following instructions remain in the same instruction set state and branch to a value written to
the PC:
— B, BL, CBNZ, CBZ, CHKA, HB, HBL, HBLP, HBP, TBB, and TBH
— in ThumbEE state, load/store instructions that fail their null check.
The definition of each of these instructions ensures that the value written to the PC is correctly
aligned for the current instruction set state.
The BLX (immediate) instruction switches between ARM and Thumb states and branches to a value
written to the PC. Its definition ensures that the value written to the PC is correctly aligned for the
new instruction set state.
The following instructions write a value to the PC, treating that value as an interworking address with
low-order bits that determine the new instruction set state and an address to branch to:
— BLX (register), BX, and BXJ
— LDR, and LDRT instructions with equal to the PC
— POP and all forms of LDM except LDM (exception return), when the register list includes the PC
— in ARM state only, ADC, ADD, ADR, AND, ASR (immediate), BIC, EOR, LSL (immediate), LSR
(immediate), MOV, MVN, ORR, ROR (immediate), RRX, RSB, RSC, SBC, and SUB instructions with
equal to the PC and without flag setting specified.
For details of how an interworking address specifies the new instruction set state and instruction
address, see Pseudocode details of operations on ARM core registers on page A2-12.
Note
— The LDR, LDRT, POP, and LDM instructions first have this behavior in ARMv5T.
— The instructions listed as having this behavior in ARM state only first have this behavior in
ARMv7.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B1-11