ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
Instruction Details
VQRDMULH. {,} , Encoding T1 / A1, Q = 1
VQRDMULH. {,} , Encoding T1 / A1, Q = 0
VQRDMULH. {,} , Encoding T2 / A2, Q = 1
VQRDMULH. {,} , Encoding T2 / A2, Q = 0
where:
See Standard assembler syntax fields on page A8-7. An ARM VQRDMULH instruction
must be unconditional.
The data type for the elements of the operands. It must be one of:
S16 encoded as size = 0b01
S32 encoded as size = 0b10.
, The destination vector and the first operand vector, for a quadword operation.
, The destination vector and the first operand vector, for a doubleword operation.
The second operand vector, for a quadword all vector operation.
The second operand vector, for a doubleword all vector operation.
The scalar for either a quadword or a doubleword scalar operation. If is S16, Dm
is restricted to D0-D7. If is S32, Dm is restricted to D0-D15.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
round_const = 1 > esize, esize);
Elem[D[d+r],e,esize] = result;
if sat then FPSCR.QC = ‘1’;
Exceptions
Undefined Instruction.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-713