ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Controlling entry to Jazelle state
The System Level Programmers’ Model
The normal method of entering Jazelle state is using the BXJ instruction, see Jazelle state entry instruction,
BXJ on page A2-74. The operation of this instruction depends on both:
the value of the JMCR.JE bit, see Jazelle Main Configuration Register (JMCR) on page A2-77
the value of the JOSCR.CV bit.
When the JMCR.JE bit is 0, the JOSCR has no effect on the execution of BXJ instructions. They always
execute as BX instructions, and there is no attempt to enter Jazelle state.
When the JMCR.JE bit is 1, the JOSCR.CV bit controls the operation of BXJ instructions:
If CV == 1 The Jazelle extension hardware configuration is valid and enabled. A BXJ instruction causes
the processor to enter Jazelle state in SUBARCHITECTURE DEFINED circumstances, and
execute bytecode instructions as described in Executing BXJ with Jazelle extension enabled
on page A2-75.
If CV == 0 The Jazelle extension hardware configuration is not valid and therefore entry to Jazelle state
is disabled.
In all SUBARCHITECTURE DEFINED circumstances where, if CV had been 1 the BXJ
instruction would have caused the Jazelle extension hardware to enter Jazelle state, it
instead:
enters a Configuration Invalid handler
sets CV to 1.
A Configuration Invalid handler is a sequence of instructions that:
includes MCR instructions to write the configuration required by the EJVM
ends with a BXJ instruction to re-attempt execution of the required bytecode
instruction.
The following are SUBARCHITECTURE DEFINED:
how the address of the Configuration Invalid handler is determined
the entry and exit conditions of the Configuration Invalid handler.
In circumstances in which the Jazelle extension hardware would not have entered Jazelle
state if CV had been 1, it is IMPLEMENTATION DEFINED whether:
the Configuration Invalid handler is entered
a SUBARCHITECTURE DEFINED handler is entered, as described in Executing BXJ with
Jazelle extension enabled on page A2-75.
In ARMv7, the JOSCVR.CV bit is set to 0 on exception entry for all implementations other than a trivial
implementation of the Jazelle extension.
The intended use of the JOSCR.CV bit is:
1. When a context switch occurs, JOSCR.CV is set to 0. This is done by the operating system or, in
ARMv7, as the result of an exception.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B1-79