ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
The format of the DBGOSSRR is:
31 0
OS Save or Restore value
OS Save or Restore value, bits [31:0]
After a write to the DBGOSLAR to lock the debug registers, the first access to the
DBGOSSRR must be a read:
when performing an OS Save sequence this read returns the number of reads from to
the DBGOSSRR that are needed to save the entire debug logic state
when performing an OS Restore sequence the value of this read is UNKNOWN and
must be discarded.
After that first read access:
a read of this register returns the next debug logic state value to be saved
a write to this register restores the next debug logic state value.
Before accessing the DBGOSSRR, you must write to the DBGOSLAR to set the OS Lock, see OS Lock
Access Register (DBGOSLAR) on page C10-75. This write to the DBGOSLAR resets the internal counter
for the OS Save or Restore operation.
The result is UNPREDICTABLE if:
you access the DBGOSSRR when the OS Lock is not set
after setting the OS Lock, the first access to the DBGOSSRR is not a read.
See The OS Save and Restore mechanism on page C6-8 for a description of using the OS Save and Restore
mechanism registers.
C10.6.4 Event Catch Register (DBGECR)
The Event Catch Register, DBGECR, configures the debug logic to generate a debug event when the OS
Lock is unlocked.
The DBGECR is:
debug register 9, at offset 0x024
a read/write register
only defined in v7 Debug
when the Security Extensions are implemented, a Common register.
In v6 Debug and v6.1 Debug, register 9 is not defined.
C10-78 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B